会议专题

IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT'10)

总文献量: 28篇会议类型: 国际会议会议地点: 上海主办单位: IEEE会议日期: 2010-12-05

文章浏览

A Comprehensive Functional Time Expansion Model Generation Method for Datapaths Using Controllers

Toshinori HOSOKAWA Teppei HAYAKAWA Masayoshi YOSHIMURA

Keynote Speech Low-Power Testing for Low-Power Devices

Xiaoqing Wen

Study on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique

Masayuki Arai Yoshihiro Tabata Kazuhiko Iwasaki

Experimental Evaluation of Hybrid RTL Scan Design

Seiji Hirota Ke Wang Yuki Yoshikawa Hideyuki Ichihara Tomoo Inoue

Network-on-Chip Concurrent Error Recovery Using Functional Switch Faults

Naghmeh Karimi Somayeh Sadeghi Zainalabedin Navabi

Multi Level Test Package A Package for C/C++ Gate Level Fault Simulation of System Level Design

S.Sadeghi F.Javaheri S.Mahmoodi Z. Navabi

Test Scheduling of Modular System-on-Chip under Capture Power Constraint

Jaynarayan Tudu Erik Larsson Virendra Singh

Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability

Kiyonori MATSUMOTO Kazuteru NAMBA Hideo ITO

An Optimal HDL-based Approach for Mixed-Ievel Hierarchical Fault Simulation

Nastaran Nemati Arezoo Kamran MohammadHossein Sargolzaie MohammadHashem Haghbayan Zainalabedin Navabi

Design for Efficient Speed-Binning and Circuit Failure Prediction and Detection

Songwei Pei Huawei Li Xiaowei Li

A New Class of Acyclically Testable Sequential Circuits with Multiplexers

Nobuya Oka Yuki Yoshikawa Hideyuki Ichihara Tomoo Inoue

Fast Detection and Analysis Schemes for System-in-Package in the Presence of RAM

Chia-Yi Lin Yu-Wei Chen Wang-Jin Chen Hung-Ming Che

A Simulation-Based Feature Selection Approach for Test Point Selection in HDL Models

Nastaran Nemati Seyyed Ehsan Mahmoudi Amirhossein Simjour Zainalabedin Navabi

Functional Fault Model for Micro Operation Faults of High Correlation with Stuck-At Faults

Chia Yee OOI Hideo FUJIWARA

SREEP-2:SR-Equivalent Generator for Secure and Testable Scan Design

Katsuya Fujiwara Hideo Fujiwara Hideo Tamamoto

Checking Pipelined Distributed Global Properties for Post-silicon Debug

Erik Larsson Bart Vermeulen Kees Goossens

A Practical and Efficient Metbod to Test for Bridging Defects

Cynthia Hao Colin D.Renfrew

Low-Power DLL-based On-Product Clock Generation for 3D Integrated Circuit Testing

Michael Buttrick Sandip Kundu

A Scalable Test Access Mechanism for Godson-T Multi-core Processor

LuningKong Yu Hu XiaoweiLj

X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme

K. Miyase F.Wu L.Dilillo A.Bosio P.Girard X.Wen S.Kajihara