A Comprehensive Functional Time Expansion Model Generation Method for Datapaths Using Controllers
Some very large-scale integrated circuits (VLSI) have been recently designed at high-level by behavioral descriptions. Behavioral synthesis can transform behavioral descriptions to regisier transfer level circuits that consist of a controller and a datapath. In this paper sequential circuits that consist of a controller and datapath are the focus. Latency the input sequence for control signal lines. and the output sequence for status signal lines of datapaths are extractedfrom controllers. We propose a generation method of comprehensive functional time expansion models in which the extracted information is incorporated as constraints. In a conventional sequential test generation method using time expansion models with only structural information, because the search space is extremely huge for practical sequential circuits. it is difficult to achieve high fault efficiency with reasonable time. In a sequential test generation method using functional time expansion models from functional verification patterns, because all the functional behavior cannot be covered, it is difficult to improve fault efficiency. Because the proposed method can cover all the functional behavior it is possible to achieve high fault efficiency with reasonable time compared to conventional methods. The proposed test generation method is applied to a divider circuit. The experimental results show that the fault efficiency is achieved to 100％ with 16 second.
n-state transition cover functional time expansion models datapath circuits constrained sequential test generation
Toshinori HOSOKAWA Teppei HAYAKAWA Masayoshi YOSHIMURA
College of Industrial Technology Nihon University 1-2-1,Izumicho,Norashino,Chiba 275-8575,Japan Graduate School of Industrial Technology Nihon University 1-2-1,Izumicho,Norashino,Chiba 275-8575,Ja Graduate School of Information Science and Electrical Engineering Kyushu University 774,Motooka Nish
国际会议
IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)
上海
英文
131-137
2010-12-05（万方平台首次上网日期，不代表论文的发表时间）