Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability

摘要：

Scan archrtecture is one of designs for tests In this architecture, all or some of flip-flops in a circuit are serially connected and form a scan chain. Chiba-scan test patters of which we try to reduce, is one of scan architectures for delay tesOng. Chiba-scan has many advantages; e.g. small area overhead as the standard scan architecture and the complete fault coverage for robust testable path delay faults However, the number of test vectors is much larger than that of other scan architectures. This paper presents a test vector reduction method for Chiba-scan. in which scan flip-flops are reordered. The experimental results give evidence that the proposed method reduces the number of test vectors by 18.4％ for ISCAS89 benchmark circuits Furthermore, the proposed method provides testing with shorter test application time and lower required ATE memory size than enhanced scan architecture.

关键词： delay fault test path delay fault two-pauern testing scan architecture Chiba-scan

作者: Kiyonori MATSUMOTO Kazuteru NAMBA Hideo ITO

作者单位: Graduate School of Advanced Integration Science,Chiba University 1-33 Yayoicho.Inage-ku,Chiba-shi,Chiba 263-8522 Japan

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 111-116

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）