Design for Efficient Speed-Binning and Circuit Failure Prediction and Detection

摘要：

With the continual scaling of semiconductor process technology. the circuit timing is increasingly impacted by process variations. It is thus important to categorize the high speed digital circuits into multple bins of different performances However, the speed-binning process typically needs very long test application time. In this paper, we proposed a design for speed binning technique, which can accomplish performance grading with short test application time. A lugh confidence of speed binning can also be provided by the proposed technique. Furthermore, the proposed technique can be used for on-line circuit failure prediction and detection Experiment results are presented to validate the proposed technique.

关键词： Speed-binning Failweprediction Failure detection Stability checker Binning indicator

作者: Songwei Pei Huawei Li Xiaowei Li

作者单位: Key Laboratory of Computer System and Architecture,Institute of Computing Technology Chinese Academy Graduate University of Chinese Academy of Sciences,Beijing,China Key Laboratory of Computer System and Architecture,Institute of Computing Technology Chinese Academy

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 161-166

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）