Low-Power DLL-based On-Product Clock Generation for 3D Integrated Circuit Testing
3D integration of ICs is an emerging technology where multiple silicon dies are stacked vertically. The manufacturing itself is based on wafer-to wafer bonding, die-to-wafer bonding or die-to-die bonding. Wafer-to-wafer bonding has the lowest yield as a good die may be stacked against a bad die, resuking in a wasted good die. Thus the lstter two options are preferred to keep yield high and manufacturing costs low. However, these methods require dies to be tested separately before they are stacked. A problem with testing dies separately is that the clock network of a prebond die may be incomplete before stacking. In this paper we present a solution to address this problem. The solution is based on on-die DLL implementations that are only activated during testing on unstacked dies to synchronize disconnected clock regions. A problem witb using DLLs in testing is tbat they cannot be turned on or off withiD a single cycle. Since scan-based testing requires that test patterns be scanned in at a slow clock frequency before fast capture clocks are applied on product clock generation (OPCG) must be used. The proposed solution addresses the above problems. Furthermore, we show that a higher-speed DLL is better suited to not only high frequency system clocks, but to lower power as well due to a smaller variable delay line.
3D Integnated Circua Testing Delay Lock Loops Low Power Testing On-product Clock Generation
Michael Buttrick Sandip Kundu
Department of Electrical and Computer Engineering University of Massacbusetts Amherst,United States
国际会议
IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)
上海
英文
153-156
2010-12-05（万方平台首次上网日期，不代表论文的发表时间）