Test Scheduling of Modular System-on-Chip under Capture Power Constraint

摘要：

Testing of an System-on-Chip (SoC) often produces larger switching activity than the functional mode. This causes power droop due to which a good chip mayfail the test that leads to yield loss. The problem becomes severe when multiple cores in an SoC, scheduled together, apply test vectors and capture test response simultaneously. i.e., when capture cycle coincide. This paper proposes a methodology to schedule cores under capture power constraint. The proposed methodology minimizes test time under capture power constraint.

作者: Jaynarayan Tudu Erik Larsson Virendra Singh

作者单位: Computer Design and Test Laboratory Indian Institute of Science, Bangalore,India Department of Computer and Information Science Linkoping University, Sweden Computer Design and Test Laboratory Indian Institute of Science,Bangalore,India

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 55-59

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）