Network-on-Chip Concurrent Error Recovery Using Functional Switch Faults

摘要：

This paper presents an error recovery scheme for the switches of Network-on-Chip (NoC) architecmrex In the proposed scheme, when a switch is reported as faulty, a robust rerouting algorithm is used to avoid routing packets through the faulty elements The fault model considered in this research is a system level fault model based on the generic properties of NoC elements functionality. The proposed error recovery scheme is evaluated in a platform using this system level fault model. The experimental results show that with a relatively low latency overhead, a large number of errors in a NoC architecture can be recovered.

关键词： NoC Error Recovery High Level Fault Model

作者: Naghmeh Karimi Somayeh Sadeghi Zainalabedin Navabi

作者单位: ECE Department University of Tehran Tehran,Iran

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 75-80

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）