Keynote Speech Low-Power Testing for Low-Power Devices
Low-power devices are indispensable for modem electronic applications, and numerous hardware/software techniques have been developed for drastically reducing functional power dissipation. However, the testing of such low-power devices has increasingly become a severe challenge, especially in at-speed scan testing where a transition is launched at the output of a flip-flop and the corresponding circuit response is captured by a flip-flop with a functional clock pulse. The reason is that most or all of the functional constraints with respect to circuit operations and clocking are ignored in at-speed scan testing, which may result in test power that is several times higher than functional power.
Xiaoqing Wen
Department of Computer Systems and Engineering Kyushu Institute of Technology Iizuka, Fukuoka 820-8502, Japan
国际会议
IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)
上海
英文
3-4
2010-12-05(万方平台首次上网日期,不代表论文的发表时间)