Study on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique

摘要：

In this study we evaluate the effectiveness of a reconfigurable design-for-debug scheme, in terms of hardware overhead and detection capability of bugs. For target circuit under debug, we first design and implement a multiprocessor system consisting of four 32-bit processor cores. and then evaluate the hardware overhead of design-for-debug circuit The evaluation result changing the arrangement of debug circuit indicates that the hardware overhead of debug circuit against the implemented multi-processor system was in the range of 8.6％ to 12.7％. Next we evaluate whether a fault effect can be observed or not by using debug circuit On a 16bit processor core we inject 10 different faults and checked whether a fault is observed at each observation point in the processor core, measuring the number of clock cycles required for observation. We also evaluated the rate of observability of each fault as well as observability of each observation point.

关键词： on-chip debug sillcon debug post-silicon vlidation design-for-debug

作者: Masayuki Arai Yoshihiro Tabata Kazuhiko Iwasaki

作者单位: Faculty of System Design,Tokyo Metropolitan University Graduate School of System Design,Tokyo Metrop Graduate School of System Design,Tokyo Metropolitan University 6-6,Hino,Tokyo 191-0065,Japan

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 47-50

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）