SREEP-2:SR-Equivalent Generator for Secure and Testable Scan Design

摘要：

It is important to find an efficient design-for testability methodology that satisfies both security and testability though there exists an inherent contradichon between security and testability for digital circuits. The authors reported a secure and testable scan design approach by using extended shift registers that are functionally equivalent but not structurally equivalent to shift registers 1141, and clarified the cardinality of shift-register equivalents (SR equivalents) to evaluate the security level 1151. In this paper, we present how to apply SR-equ,valent circuits to scan design so that the modified scan designed circuits are both secure and testable. We consider how to design SR-equivalent circuits under several constraints and how to control/observe SR equivalent arcuits to guarantee easy scan-in/out operations We also discuss how secure the modified scan designed circuits are. A program called SREEP-2 is presented to solve tbose problems.

关键词： design-for-tesmbility scan design shift register equivalents security scan-based side-channel attack.

作者: Katsuya Fujiwara Hideo Fujiwara Hideo Tamamoto

作者单位: Dept of Computer Science and Engineering Akita University Akita, 010-8502,JAPAN Graduate School of Information Science Nara Institute of Science and Technology Nara,630-0192,JAPAN Dept of Computer Science and Engineering Akita University Akita,010-8502,JAPAN

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 7-12

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）