会议专题

The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

总文献量: 79篇会议类型: 国际会议会议地点: 北京主办单位: 中科院计算技术研究所会议日期: 2007-10-08

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Using FPGA configuration memory to accelerate yield learning for advanced process

Jenny Fan Xiao-Yu Li Ismed Hartanto

An Improved Test Case Generation Method of Pair-Wise Testing

Qian Feng-an Jiang Jian-hui

Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC

LiquanFang Yang Zhong Henk van de Donk Yizi Xing

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition

Aiman H. El-Maleh Mustafa Imran Ali Ahmad A Al-Yamani

EHSAT Modeling from Algorithm Description for RTL Model Checking

Xiaoqing Yang Jinian Bian Shujun Deng Yanni Zhao

Programmable Scan-Based Logic Built-In Self Test

Liyang Lai Wu-Tung Cheng Thomas Rinderknecht

On Generating Vectors That Invoke High Circuit Delays-Delay Testing and Dynamic Timing Analysis

I-De Huang Sandeep K. Gupta

Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis

Sying-Jyan Wang Xin-Long Li Katherine Shu-Min Li

Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

F. Azais L. Larguier M. Renovell

Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Minjin Zhang Xiaowei Li

Simulating Open-Via Defects

Stefan Spinner Jie Jiang Ilia Polian Piet Engelke Bernd Becker

A RTL Testability Analyzer Based on Logical Virtual Prototyping

Yu Huang Nilanjan Mttkherjee Wu-Tung Cheng Greg Aldrich

Enhanced Broadside Testing for Improved Transition Fault Coverage

Irith Pomeranz Sudhakar M. Reddy

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults

Yuki Yoshikawa Satoshi Ohtake Hideo Fujiwara

An Accurate Analysis of Microprocessor Design Verification

Haihua Shen Heng Zhang

Programmable Logic BIST for At-speed Test

Yu Huang Xijiang Lin

Test Scheduling for Memory Cores with Built-In Self-Repair

Tomokazu Yoneda Yuusuke Fukuda Hideo Fujiwara

Block Marking and Updating Coding in Test Data Compression for SoC

Lei Zhang Huaguo Liang Wenfa Zhan Cuiyun Jiang

SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges

Piet Engelke Bettina Braitling Ilia Polian Michel Renovell Bernd Becker

Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost

Dong Xiang Krishnendu Chakrabarty Dianwei Hu Hideo Fujiwara