Using FPGA configuration memory to accelerate yield learning for advanced process

摘要：

The configuration memory is irregularly placed in a FPGA (Field Programmable Gate Array) chip and physically attached to the programmable logic circuits. This type of memory is more powerful than standard SRAM to monitor random or systematic process defects because the configuration memory test catches defects in both the memory cell and logic circuits. This paper will demonstrate a methodology of using this capability to accelerate yield learning for advanced process.

关键词： Bit map Configuration memory FPGA Memory fail signature Yield improvement.

作者: Jenny Fan Xiao-Yu Li Ismed Hartanto

作者单位: Xilinx Inc.

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 505-508

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）