Simulating Open-Via Defects

摘要：

Open-via defects are a major systematic failure mechanism in nanoscale manufacturing processes. We present a flow for simulating open-via defects. Electrical parameters are extracted from the layout and technology data and represented in a way which allows efficient simulation on gate level. The simulator takes oscillation caused by open-via defects into account and quantifies its impact on defect coverage. The flow can be employed for manufacturing test as well as for defect diagnosis.

关键词： Open-via defects Fault simulation Defect modeling

作者: Stefan Spinner Jie Jiang Ilia Polian Piet Engelke Bernd Becker

作者单位: Computer Architecture Group Institute for Computer Science Albert-Ludwigs-University Georges-Kohler-Allee 51 D-79110 Freiburg i. Br., Germany

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 265-270

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）