Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits

摘要：

This paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called Minimum Switch Condition is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called Signal Coherence Condition is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunction. DFT and ATPG recommendations are derived from this analysis.

作者: F. Azais L. Larguier M. Renovell

作者单位: LIRMM, CNRS/University of Montpellier, 161 rue Ada-34392 Montpellier Cedex 5-France

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 239-244

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）