An Accurate Analysis of Microprocessor Design Verification
Comparing with the passion for verification technical innovations, the practical verification experiences especially the bug reports and analyses rarely appear in public research. It is very important to analyze the practical bug reports for feedback on the future verification. Thanks to the sufficient design scale of our microprocessor and efficient verification environment we developed, we are able to present in this paper an extensive analysis of the effects of bugs on different design stages and different microarchitectures. The analysis approaches and results are valuable for estimating the distribution of bugs in a microprocessor design and preventing the project from verification bottlenecks.
Haihua Shen Heng Zhang
Institute of Computing Technology Chinese Academy of Sciences Beijing, China
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
165-171
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）