Programmable Logic BIST for At-speed Test
In this paper, we propose a novel programmable logic BIST controller that can facilitate at-speed test for the design with multiple clock domains and multiple clock frequencies. Moreover, a static analysis method is also proposed to optimize the BIST test pattern allocation for testing the timing faults in different intra/inter clock domains when the maximum number of applied BIST test patterns is specified. Experimental results show the effectiveness of the proposed method on achieving higher test coverage than the method with test patterns evenly distributed among different test sessions.
Yu Huang Xijiang Lin
Mentor Graphics Corp. 300 Nickerson Road Marlborough, MA 01752 Mentor Graphics Corp. 8005 SW Boeckman Rd Wilsonville, OR 97068
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
295-300
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）