Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
In this paper, we propose a layout-aware scan tree synthesis methodology. Scan tree can greatly reduce test data volume, which is very desirable in SOC testing. However, previous researches on scan tree synthesis have not considered routing issues in physical design, which may create a tree with excessively long routing path. In this paper we present a multi-layer multi-level scan tree synthesis method, in which both data compression and routing length are taken into account. Experimental results show that the proposed test method achieves high compression rate with limited routing overhead.
Sying-Jyan Wang Xin-Long Li Katherine Shu-Min Li
Dep. of Computer Science and Engineering National Chung Hsing University Taichung, Taiwan, ROC Dept. of Computer Science and Engineering National Sun Yat-Sen University Kaohsiung, Taiwan, ROC
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
129-132
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）