Transaction Level Formal Verification using Timed Automata

摘要：

In this paper a formal methodology is proposed to verify TLM-2.0 designs. In this approach TLM-2.0 designs are translated into Timed Automata formal modeL Several properties are defined by which the verification will be performed and a fault-model is introduced to evaluate these properties which mimics the transaction level design errors The properties are then verified on the Timed Automata representation of the system against the faults using the formal verifier of the UPPAAL tooL The efficiency of the approach is illustrated by a case study.

关键词： formal verification timed automatta transaction level modeling UPPAAL

作者: A.Ghofrani F. Javaheri H. Noori Z. Navabi

作者单位: Electrical and Computer Engineering Department University of Tehran Tehran, Iran

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 41-46

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）