VPLib: A Hybrid Method to Verify Microprocessor Prototypes on FPGA

摘要：

FPGA prototyping is widely used in Microprocessor design and verification because of its high performance and low cosL But the low observability has makes debugging an insurmountable task This paper suggests switching the failed test on FPGA to SW-simulation to increase observability. As is shown in our work the huge amount of tests can benefit from the at-speed FPGA without much overhead to re-run a small proportion of the failed ones. By using a VerificaOon Purpose Library. VPLib, consisted of a set of test-specific APls the proposed method provides a umfied interface to create platform independent tests. We assess the feasibility of our approach by applying the method to a 32bit RISC microprocessor designed by our institute.

关键词： Microprocessor Verification FPGA Veriflcatioon Purpose Library Verification Purpose Operating System

作者: Jingfen LU Lingkan GONG Peng MA

作者单位: Dept.of IC Design East China Institute of Computer Technology Shanghai,China

会议类型: 国际会议

会议名称: IEEE 11th Workshop on RTL and High Level Testing(第11届IEEE寄存器传输级与高层次测试国际研讨会 WRTLT10)

会议地点: 上海

会议语种:英文

页码: 51-54

在线出版日期: 2010-12-05（万方平台首次上网日期，不代表论文的发表时间）