Aggressive Design of Ultra-Shallow Junction for Near-Scaling-Limit Bulk Planar CMOS by using Raised Source/Drain Extension Structure and Carbon Co-Implantion Technology
An aggressive junction design concept is proposed for further scaling of bulk planar CMOS featuring selectively epi-grown raised source/drain extensions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process and carbon co-implantation. The junction design window enlarged by introducing the RSDext enables us to elaborately control slight intentional diffusion through the newly developed MSA process rather than aiming complete-diffusion-less junctions. Such the effective ultra-shallow junctions under the RSDext realized both lower parasitic resistance and lower junction leakage by eliminating current bottleneck and implant defects while maintaining superior short-channel-effect suppression. Cluster carbon co-implanted RSDext structure, which enables high boron concentration at the silicide interface and low deep halo dosage, was also effective to reduce parasitic resistance and junction leakage. We demonstrated sub-30 nm gate length CMOSFETs with one decade reduction of junction leakage, and 10％ Ion improvement for both N and PFET by adapting closely positioned silicide to the gate edge (about 5 nm).
K. Uejima K. Yako T. Yamamoto N. Ikarashi S. Shishiguchi T. Hase M. Hane
Renesas Electronics Corporation Renesas Electronics America, Inc.
国际会议
2010 International Workshop on Junction Technology(2010国际结技术学术研讨会 IWJT 2010)
上海
英文
1-6
2010-05-10（万方平台首次上网日期，不代表论文的发表时间）