Grain Boundary Barrier Height and Threshold Voltage Model of Polycrystalline Silicon Thin Film Transistors

摘要：

Temperature effect of grain boundary barrier height is simulated considering double exponentials distribution trap states. Two threshold voltage definitions are compared, gate voltage when maximum barrier height occurs and when the condition of equal trapped and free charge interface. And grain size dependence of threshold voltage is also present and compared. Low electric field mobility is computed based on the barrier height model. The results show that barrier height is less dependent on temperature, and more dependent on the trap states density or grain size.

作者: Hongyu He Xueren Zheng

作者单位: Institute of Microelectronics, School of Electronic and Information Engineering, South China Univers Institute of Microelectronics, School of Electronic and Information Engineering, South China Univers

会议类型: 国际会议

会议名称: 2010 International Workshop on Junction Technology(2010国际结技术学术研讨会 IWJT 2010)

会议地点: 上海

会议语种:英文

页码: 1-4

在线出版日期: 2010-05-10（万方平台首次上网日期，不代表论文的发表时间）