Investigation of Wafer Temperature Effect During Implant for PMOS Transistor Fabrication
The temperature effect for buried channel PMOS transistor characteristics was investigated. Generally, only dose, energy and implant angle have been considered as the major parameters for process matching between different high current implanters in transistor manufacturing. However, as the device is scaled down to sub-100nm size, additional parameters such as instantaneous dose rate and wafer temperature have become increasingly important for controlling the dopant profile by changing the annealing behavior of defects. By changing the wafer temperature, the threshold voltage (VT) changed dramatically while the active area sheet resistance remained constant. The peak height of both the boron and fluorine profiles corresponding to the location of the amorphous/crystalline (a/c) interface increased proportionally with increasing wafer temperature and to a lesser degree with increasing instantaneous dose rate. This higher secondary peak height resulted in reduced lateral diffusion, shorter effective channel length, and therefore a lower threshold voltage (VT).
Tae-Hoon Huh Dong-Chul Park Byung-Jae Kang Geum-Joo Ra Shin-Woo Kang Steve Kim Ron Reece Leonard M.Rubin Min-Sung Lee Jong-Oh Lee
Axcelis Technologies Inc., 108 Cherry Hill Drive, Beverly, MA 01915, USA Samsung Electronics Co., LTD., San＃16 Banwol-Dong, Hwasung-City, Gyeonggi-Do, Korea
国际会议
2008 International Workshop on Junction Technology(第六届结技术国际研讨会)
上海
英文
39-42
2008-05-15（万方平台首次上网日期，不代表论文的发表时间）