Novel Diffusion-less Ultra-Shallow Junction Engineering based on Millisecond Annealing for Sub-30nm Gate Length Planar Bulk CMOSFET
The formation of ultra-shallow junction (USJ) less than 10 nm by using diffusion-less high-activation millisecond annealing technique has been investigated for deeply scaled planar bulk CMOS. This achievement relies on cross-sectional visualization of impurity distributions in MOSFET based on the electron beam holography technology with extremely high spatial resolution.Incorporation of cluster-ion (B18H22) implantation for PFETs and high-temperature millisecond-annealing, where the dedicated fabrication-process was redesigned including multiple halo implantation and thin S/D-silicidation, enables us to examine near-scaling limit bulk CMOS device performance with ultimately shallow junction.Furthermore, the parasitic resistance reduction with optimized spacing of the bottleneck at the joint of S/D-extension and deep-S/D junction was developed to overcome trade-off between the functionable minimum gate length (Lmin) and on-current (Ion) of MOSFET. Those techniques that realize fully low parasitic resistance and ultimately shallow xj extend Lmin scaling to less than 30 nm for planar bulk CMOS devices.
K.Uejima K.Yako N.Ikarashi M.Narihiro M.Tanaka T.Nagumo A.Mineji S.Shishiguchi M.Hane
Devices Platforms Research Laboratories, NEC Corporation NEC Electronics Corporation
国际会议
2008 International Workshop on Junction Technology(第六届结技术国际研讨会)
上海
英文
62-67
2008-05-15（万方平台首次上网日期，不代表论文的发表时间）