Embedded Silicon Germanium (eSiGe) technologies for 45nm nodes and beyond
This paper reviews main technologies of embedded Silicon Germanium (eSiGe) for 45nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550℃ to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface pre-cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. The final item to be considered carefully is Boron concentration in eSiGe, bacause excessive Boron compensates the strain in eSiGe as well as carbon. Finally We demonstrated the /on= 0.795mA/μm@/off=100nA/μm using above key techniques and an item.
Naoyoshi Tamura Yosuke Shimamune Hirotaka Maekawa
Advanced Process Development Department Silicon Technology Development Laboratories Fujitsu Laboratories, LTD.Fuchigami 50, Akiurno, Tokyo, 197-0833, Japan
国际会议
2008 International Workshop on Junction Technology(第六届结技术国际研讨会)
上海
英文
73-77
2008-05-15（万方平台首次上网日期，不代表论文的发表时间）