Laser Spike Annealing for Advanced CMOS Devices
The introduction of new materials in recent years puts more stringent requirements on thermal budget management. For example, high Ge concentration in e-SiGe used for strain engineering makes wafers prone to thermal plastic deformation which limits the maximum annealing temperature. In this paper, we will explore ways to expand the process window using sub-millisecond laser spike annealing. Focus will be placed on thermal budget reduction and its impact on wafer warpage, Rs-Xj scaling and cross die temperature uniformity. Compatibility with high-k/metal gates and future non-planar device structures will also be discussed.
Yun Wang Shaoyin Chen Michael Shen Xiaoru Wang Senquan Zhou Jeff Hebb David Owen
Ultratech Inc., San Jose, California, 95134, USA
国际会议
2008 International Workshop on Junction Technology(第六届结技术国际研讨会)
上海
英文
126-130
2008-05-15（万方平台首次上网日期，不代表论文的发表时间）