Eztendibility of NiPt Silicide to the 22-nm Node CMOS Technology

摘要：

This paper shows ultra-low contact resistivities with standard NiPt silicide process that can reach 1 × 10(-8) Ω-cm2 for both n+ and p+ Si by using novel test structures of small silicided contact with varied areas from 20-nm diameter to 260-nm diameter by e-beam lithography fabricated on highly doped substrate made by conventional source drain implantation. It demonstrates that NiPt silicide can fulfill CMOS technology requirements down to the ITRS 22nm node.

作者: Kazuya Ohuchi John Bruley Gilbert U.Singco Francois Pagette Anna W.Topol Michael J.Rooks James J.Bucchignano Vijay Narayanan Mukesh Khare Mariko Takayanagi Kazunari Ishimaru Christian Lavoie Dae-Gyu Park Ghavam Shahidi Paul M.Solomon Conal E.Murray Chris P.DEmic Isaac Lauer Jack O.Chu Bin Yang Paul Besser Lynne M.Gignac

作者单位: Toshiba America Electronic Components Inc., IBM SRDC, Hopewell Junction, NY 12533 International Business Machine Corporation, IBM Research Division, T.J.Watson Research Center, Yorkt Toshiba America Electronic Components Inc., T.J.Watson Research Center, Yorktown Heights, NY 10598 International Business Machine Corporation, IBM Research Division, T.J.Watson Research Center, Yorkt Advanced Micro Devices, T.J.Watson Research Center, Yorktown Heights, NY 10598 Advanced Micro Devices, Inc., Sunnyvale, CA 94088

会议类型: 国际会议

会议名称: 2008 International Workshop on Junction Technology(第六届结技术国际研讨会)

会议地点: 上海

会议语种:英文

页码: 150-153

在线出版日期: 2008-05-15（万方平台首次上网日期，不代表论文的发表时间）