Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation
Functional test sequences were shown to detect defects that are not detected by structural tests. They also help in avoiding overtesting. However, fault simulation to compute the stuck-at fault coverage of functional test sequences can be time consuming especially in applications where a large number of test sequences need to be evaluated and compared. To obtain fast yet accurate estimates of the stuck-at fault coverages of functional test sequences, we describe a fault coverage metric based only on logic simulation of the gate level circuit. The metric is based on the set of states that the circuit traverses under the test sequence. We define several versions of the metric suitable for different applications. We present experimental results demonstrating the effectiveness of the metric for ranking of test sequences based on their fault coverage.
Irith Pomeranz Praveen K. Parvathala Srinivas Patil
School of ECE Purdue University W. Lafayette, IN 47907, U. S. A. Test Technology Intel Corp. Chandler, AZ, U. S. A. Test Technology Intel Corp. Austin, TX, U.S.A
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
25-30
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）