Using Programmable On-Product Clock Generation (OPCG) for Delay Test

摘要：

On-product clock generation (OPCG) has been used for many years, often in conjunction with Logic and Memory BIST, but it is a labor-intensive process to identify the cut points and the OPCG behavior so the ATPG tools can ignore the OPCG logic. Supporting programmable OPCG logic in an ASIC methodology flow required us to automate the OPCG test generation flow. This paper describes how we provide a means for dealing with the programmable aspects of OPCG for use during ATPG and show some results for a few real designs.

作者: Brion Keller Anis Uzzaman Bibo Li Tom Snethen

作者单位: Cadence Design Systems, Inc., Endicott, New York 13760

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 69-72

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）