An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits

摘要：

This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.

关键词： delay fault online testing BIS techniques robust delay test design for testability

作者: Elham K. Moghaddam Shaahin Hessabi

作者单位: Department of Computer Engineering, Sharif University of Technology, Tehran, IRAN

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 73-76

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）