An Efficient Peak Power Reduction Technique for Scan Testing
Power management is posing serious challenges for scan-based testing. In this paper, we propose a low power test pattern generation technique which minimizes the peak power consumption associated with the scan and capture operations. Given a set of fully specified test patterns, the proposed technique iteratively replaces the high power consumption patterns with low power ones generated by a PODEM- based low power ATPG. The proposed technique has been validated using ISCAS89 benchmark circuits. Compared to a commercial ATPG using high merge ratio and random-fill options, the proposed technique reduces the peak shift and capture power by 27.3％ and 19.6％, respectively, and the average power by 49.9％.
Meng-Fan Wu Kai-Shun Hu Jiun-Lang Huang
Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University, Taipei 106, Taiwan
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
111-114
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）