High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects
Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed In addition, previous SPICE based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To overcome this problem, we also develop a new high-level test pattern generation method by using the abstract signal integrity fault model. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE- based pattern generation method
signal integrity interconnect test RLC interconnect model fault modeling
Sunghoon Chun Yongjoon Kim Sungho Kang
Department of Electrical and Electronic Engineering Yonsei University 134 Shinchon-dong Seodaemoon-gu, Seoul, Korea
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
115-118
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）