Optimized Assignment Coverage Computation in Formal Verification of Digital Systems
Model checking thoroughly verifies the design correctness with respect to a specification. When the verification process succeeds, we can only postulate the correctness of the design relative to the given specification. How far can we affirm the verified design implements all the behavior of the desired system? With this regard we need to estimate the completeness of the properties by using some coverage metrics. In this paper, we have proposed a new metric called assignment coverage and an optimized method to overcome the intensive computations required for the multiple transformations among the abstract layers in the verification tool. The proposed coverage computation method provides adequate information to complete the set of properties. Finally, we have applied the proposed metric to some verification benchmark to reveal the effectiveness of this metric in finding undetected coverage holes.
Majid Nabi Hamid Shojaei Siamak Mohammadi Zainalabedin Navabi
CAD Research Group ECE Department, Tehran University ECE Department, Tehran University
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
172-177
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）