Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip

摘要：

Smaller manufacturing processes have resulted in higher power densities which put greater emphasis on packaging and temperature control during test. For system-on-chips, peak power-based scheduling algorithms are used to optimize tests while satisfying power budgets. However, imposing power constraints does not necessarily mean that overheating is avoided due to the non-uniform power distribution across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Experiments show that even minimal increases in test time can yield considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

关键词： SoC test thermal constraint wrapper design TAM design test scheduling

作者: Thomas Edison Yu Tomokazu Yoneda Krishnendu Chakrabarty Hideo Fujiwara

作者单位: Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City Electrical and Computer Engineering, Duke University, Box 90291, 130 Hudson Hall, Durham, NC 27708

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 187-192

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）