Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC
This paper introduces an efficient test access mechanism for Advanced Microcontroller Bus Architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the Advanced High-performance Bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.
Jachoon Song Juhee Han Dooyoung Kim Hyunbean Yi Sungju Park
Department of Computer Science & Engineering, Hanyang University
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
193-198
2007-10-08(万方平台首次上网日期,不代表论文的发表时间)