A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement

摘要：

In this paper, we propose a novel built-in self-test (BIST) circuit to directly measure cycle-to-cycle jitter. The clock-under-test is under-sampled by this measurement circuit and the jitter values are transformed into digital words. A time-amplified technique is applied to obtain relatively higher resolution with smaller hardware overhead. Experimental results show that our proposed circuit is able to measure the jitter providing the clock frequency up to 2 GHz with resolution of 2 picoseconds.

关键词： cycle-to-cycle jitter jitter measurement built-in serf-test mixed-signal testing time-to-digital converter

作者: Nai-Chen Daniel Cheng Yu Lee Ji-Jan Chen

作者单位: SOC Technology Center, Industrial Technology Research Institute, Hsinchu, Taiwan

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 219-223

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）