An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing
This paper describes a technique for estimating total jitter that, along with a loopback-based margining test, can be applied to test high speed serial interfaces. We first present the limitations of the existing estimation method, which is based on the dual-Dirac model. The accuracy of the existing method is extremely sensitive to the choice of the fitting region and the ratio of deterministic jitter to random jitter. Then, we propose a high-order polynomial fitting technique and demonstrate its value for a more efficient and accurate total jitter estimation at a very low Bit-Error-Rate level. The estimation accuracy is also analyzed with respect to different numbers of measurement points for fitting. This analysis shows that only a very small number (i. e., 4) of measurement points is needed for achieving accurate estimation.
Dongwoo Hong Kwang-Ting (Tim) Cheng
Department of Electrical and Computer Engineering University of California, Santa Barbara, CA 93106, USA
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
224-229
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）