Low Power Reduced Pin Count Test Methodology

摘要：

This paper explores the savings in power achieved using an I/O gating and Reduced Pin Count Test (RPCT) technique during manufacturing test. Since I/O pads consume significant power, preventing them from toggling during test will bring about a corresponding savings in power. The paper describes a fully automated RPCT methodology for low power that includes insertion of the RPCT and I/O gating logic and test generation. Based on simulation of the ATPG patterns, we show that the power consumed during scan test can be reduced significantly.

作者: Krishna Chakravadhanula Nitin Parimi Brian Foutz Bing Li Vivek Chickermane

作者单位: Cadence Design Systems, 1701 North Street, Endicott, NY 13760, USA

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 251-256

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）