Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator

摘要：

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

作者: Yoshinobu Higami Kewal K. Saluja Hiroshi Takahashi Shin-ya Kobayashi Yuzo Takamatsu

作者单位: Graduate School of Science and Engineering, Ehime University Dept. of Electrical and Computer Engineering, University of Wisconsin-Madison

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 271-274

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）