CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors
Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault- tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.
Shijian Zhang Weiwu Hu
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
313-318
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）