An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing

摘要：

To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter- clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.

作者: Xiao-Xin FAN Yu HU Laung-Temg (L.-T.) WANG

作者单位: Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acade SynTest Technologies, Inc., 505 S. Pastoria Ave., Suite 101, CA 94086, USA

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 341-346

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）