Scan Power Reduction Through Scan Architecture Modification And Test Vector Reordering
Due to higher switching activity within scan chain for scanning in/out of the stimuli/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places in the traditional scan chain, there by converting the D flip-flops into T flip-flops temporarily during scan. This approach involves reordering of test vectors but not reordering of the scan cells. Our proposed method is verified with ISCAS89 benchmark circuits, which shows that upto 34％ reduction in switching activity within modified scan architecture is possible.
scan chain scan power test vector reordering
Chandan Giri Pradeep Kumar Choudhary Santanu Chattopadhyay
Dept. of E & ECE, IIT Kharagpur, India
国际会议
The 16th Asian Test Symposium(第十六届亚洲测试学术会议)
北京
英文
419-424
2007-10-08（万方平台首次上网日期，不代表论文的发表时间）