Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique

摘要：

This paper presents a Response Inversion Scan Cell (RISC) technique to reduce the peak capture power in test mode. The RISC technique inverts the data input of selected scan cells so that peak capture power is reduced. According to the experimental data on ISCAS89 benchmark circuits, the RISC technique effectively reduces the peak capture power by 45％ at a cost of 7.6％ area overhead. The presented technique requires minimum change in the existing design for testability (DFT) methodology and it does not degrade fault coverage. The RISC technique is validated by a chip experiment on a 0.18μm low power design.

作者: Bo-Hua Chen Wei-Chung Kao Bing-Chuan Bai Shyue-Tsong Shen James C. -M. Li

作者单位: Laboratory of Dependable Systems, Graduate Institute of Electronics Engineering, National Taiwan University

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 425-430

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）