Improving Test Pattern Compactness in SAT-based ATPG

摘要：

Automatic Test Pattern Generation (ATPG) is one of the core problems in testing of digital circuits. ATPG algorithms based on Boolean Satisfiability (SAT) turned out to be very powerful, due to recent advances in SAT-based proof engines. SAT-based ATPG clearly outperforms classical approaches especially for hard-to-detect faults. But due to the SAT provers, a major drawback of the resulting test patterns is that a large number of input bits is specified. Thus, the resulting patterns are not well suited for test compaction and compression. In this paper we present techniques to increase the number of unspecified bits in test patterns generated by SAT-based ATPG tools. We make use of structural properties of the circuit and apply local dont cares. Experimental results on industrial designs show significant reductions of up to 97％.

作者: Stephan Eggersgluess Rolf Drechsler

作者单位: Institute of Computer Science, University of Bremen 28359 Bremen, Germany

会议类型: 国际会议

会议名称: The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

会议地点: 北京

会议语种:英文

页码: 445-450

在线出版日期: 2007-10-08（万方平台首次上网日期，不代表论文的发表时间）