An 8-bit 80MS/s 2b/cycle SAR ADC for sensor application

摘要：

　　This paper presents an 8-bit,80MS/s Successive Approximation Register analog-to-digital converter(SAR ADC)with 2bit/cycle structure for sensor application.By using two capacitor-DAC arrays,S-DAC and R-DAC,the proposed SAR ADC can obtain 2-bit in one comparison cycle.With splitcapacitor structure and monotonic switching strategy,two DACs reduce the number of capacitors and save the ADC power consumption.The proposed asynchronous control logic speeds up the ADC.The proposed ADC achieves 46.17dB SNDR at 80MS/s rate with 1.8V supply voltage in 180nm CMOS process.

关键词： analog-to-digital converter SAR ADC 2b/cycle split-capacitor

作者: Lei Zhang Wenzhong Lou Yige Gao

作者单位: School of Information and Electronic Beijing Institute of Technology Beijing 100081,China School of Mechatronical Engineering Beijing Institute of Technology Beijing 100081,China

会议类型: 国际会议

会议名称: The 12th International Symposium Antennas, Propagation, and EM Theory(ISAPE 2018)?(第十二届天线、传播与电磁理论国际学术会议)

会议地点: 杭州

会议语种:英文

页码: 1-4

在线出版日期: 2018-12-03（万方平台首次上网日期，不代表论文的发表时间）