Failure Analysis Examination of the Effect of Thermal Cycling on Copper-filled TSV Interposer Reliability
With the development of 3D integrated packaging,Through Silicon Via(TSV)has become one of the most promising technologies in 3D stacking package.As the important physical connection and electrical connection between the chip and chip,TSVs reliability is undoubtedly the key to determine the reliability of TSV three-dimensional integrated devices.TSV three-dimensional integrated device will gradually be failed by the thermal mechanical stress,electrical stress and other stress,which will greatly affect the TSV three-dimensional device reliability.Identifying defects and analyzing the failure mechanism are very important for the optimization and improvement of the design,production and use of TSV 3D integrated devices.In this paper,the reliability of through-silicon via(TSV)interposer under thermal cycling test was analyzed.Generation of crack along the Top RDL interface and Cu-TSV deformation were identified as two main failure modes after 1000 thermal cycles.FEM analysis was performed on TSV interposer to understand how the stress distribution in the structure affects the formation and growth of defects.The results show a good correlation between the positions of the damage observed and the simulation of stress concentration area.
Through silicon vias Failure analysis finite element analysis 3D integrated circuits
Yuan Chen Peng Zhang Wei Su Xiao ling Lin
Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The Analysis and Test Center South China University of Technology Guangzhou,China Science and Technology on Reliability Physics and Application of Electronic Component Laboratory The
国际会议
上海
英文
148-151
2018-08-08（万方平台首次上网日期，不代表论文的发表时间）