Process development and reliability for wafer-level 3D IC integration using micro-bump/adhesive hybrid bonding and via-last TSVs

摘要：

　　Wafer-level hybrid bonding and through silicon vias(TSVs)are key technologies to fabricate 3D IC products with ultra-fine pitch bumps and high interconnects density.In this work,process optimization and reliability evaluation of 3D IC integration using wafer-level micro-bump/dry film adhesive hybrid bonding and via-last TSVs were presented.In order to obtain a well hybrid bonding interface,various hybrid bonding methods,i.e.,low temperature bonding using no reflowed bump,high temperature bonding using no reflowed bump,and high temperature bonding using reflowed bump,were investigated.Key processes including dry film lamination,hybrid bonding,and via-last TSV fabrication were developed.Reliability of the hybrid bonded chips were characterized by various tests.The results indicate that wafer-level hybrid bonding with via-last TSVs approach is a reliable,simple solution to fabricate 3D IC products.

关键词： 3D IC wafer-level hybrid bonding insert Cu pillar solder bump dry film adhesive TSVs reliability

作者: Mingjun Yao Ning Zhao Daquan Yu Zhiyi Xiao Haitao Ma

作者单位: School of Materials Science and Engineering Dalian University of Technology Dalian,China Huatian Technology(Kunshan)Electronics Co.Kunshan,China

会议类型: 国际会议

会议名称: 第十九届国际电子封装技术会议(ICEPT 2018)

会议地点: 上海

会议语种:英文

页码: 241-246

在线出版日期: 2018-08-08（万方平台首次上网日期，不代表论文的发表时间）