A 0.6-V Supply Two-Step Time-to-Digital Converter Using Dynamic Threshold Technology

摘要：

　　A two-step time-to-digital converter(TDC)that achieves linear,high-speed time quantization,high-resolution under a 0.6-V supply is proposed in this paper.In order to work in low-voltage supply,dynamic threshold technology is used.The TDC mainly consists of two vernier delay-line TDCs and an array of SR-latch-based time amplifiers to achieve high resolution.This TDC is designed in a 65-nm CMOS technology.Simulation results of this TDC show that the minimum time resolution is 2.5ps while only consuming 0.5mW.The differential nonlinearity(DNL)of this proposed TDC is 0.9LSB and the integral nonlinearity(INL)is 2.3LSB.

关键词： time-to-digital converter dynamic threshold technology time amplifier

作者: Cong Zhang Zixuan Wang Xiaojuan Xia Xin Geng Yufeng Guo Zichen Tian Mei Liu

作者单位: College of Electronic and Optical Engineering & College of Microelectronics Nanjing University of Posts and Telecommunications Nanjing,China

会议类型: 国际会议

会议名称: 第十九届国际电子封装技术会议(ICEPT 2018)

会议地点: 上海

会议语种:英文

页码: 1638-1641

在线出版日期: 2018-08-08（万方平台首次上网日期，不代表论文的发表时间）