Study on the structure of vertical Through Silicon Via with aspect ratio 2.5:1 for CMOS image sensor

摘要：

　　Through Silicon Via(TSV)plays a important role as the interconnect in three dimensional miniaturization of electronic device.In this paper,the process flow of vertical TSV with aspect ratio 2.5:1 is presented for CMOS image sensor.The process includes wafer bonding,thinning,TSV etching,electroplating,wet etching,passivation,Ball Grid Array(BGA)and dicing.The measured low resistance of interconnection shows high current carrying capability of the TSVs.The simplified process provides a cost-effective solution for 3D integration.

关键词： Through Silicon Via (TSV) CMOS image sensor (CIS) Wafer Level Chip Scale Package (WLCSP)

作者: Lijun Chen Fengwei Dai Wenqi Zhang

作者单位: The National Center for Advanced Packaging 200 Linghu Boulevard,Wuxi City,Jiangsu Province,214135,P.R.China

会议类型: 国际会议

会议名称: 第十九届国际电子封装技术会议(ICEPT 2018)

会议地点: 上海

会议语种:英文

页码: 1706-1708

在线出版日期: 2018-08-08（万方平台首次上网日期，不代表论文的发表时间）