An Improved FPGA Implementation of Sparse Fast Fourier Transform

摘要：

　　The scale of the sequential data sets to be real-timely processed in most sectors of digital signal processing has substantially increased,making efficient numerical algorithms such as sparse fast Fourier transform(SFFT)more attractive than ever.This paper presents an improved FPGA-based SFFT implementation scheme,where a novel pipeline shift queue structure and a novel pipeline tracking filter structure are designed to significantly reduce the computational complexity.With the proposed scheme,millions of SFFT modules can be integrated on a single Virtex-6 FPGA chip,in addition to which,no assumptions or a priori knowledge on the spectrum distribution of the input signal is required.

关键词： Digital signal processing sparse fast Fourier transform (SFFT) hardware implementation architecture field-programmable gate array (FPGA)

作者: Xiaohe Pei Tao Shan Shengheng Liu Yuan Feng

作者单位: School of Information and Electronics,Beijing Institute of Technology,Beijing,China

会议类型: 国际会议

会议名称: 2017 6th International Conference on Advanced Materials and Computer Science (ICAMCS 2017) 2017年第六届先进材料与计算机科学国际会议(ICAMCS 2017)

会议地点: 郑州

会议语种:英文

页码: 1-9

在线出版日期: 2017-04-29（万方平台首次上网日期，不代表论文的发表时间）