Trial-n-Error: Use Application-aware DRAM Refresh Control to Squeeze the Margin of Retention Time in Hybrid Memory Cube
With the increase of storage density, DRAM refresh leads to higher overheads of power and bandwidth.Particularly in emerging Hybrid Memory Cube (HMC), the situation is exacerbated by 3D stacking technology because its high thermal dissipation density drastically shrinks the cells retention time (RT) and demands a higher refresh rate to guarantee reliability.However, the efficient inter-layer Through-Silicon-Vias and dedicated logic layer in HMC provide a great opportunity to revisit the refresh strategy.To exploit the hardware resources for a smarter solution, we propose an application-aware refresh control scheme, Trial and Error (Trial-n-Error), which leverages the data-pattern dependence characteristics of the cells retention time to reduce refresh operations.Trial-n-Error is a systematic approach that employs our proposed Synergy Testing to capture the refresh bottleneck of DRAM memory: weak cells that have a relative shorter retention time.By locating the dominant weak cells (DWCs) sensitized by applications,Trial-n-Error can avoid the worst-case refresh setting, and adapt the refresh rate under the control of our self-tuning algorithm.Therefore, Trial-n-Error can gradually approach to the possible lower-bound of refresh rate for less energy and memory bandwidth consumption in HMCs.In experiments, we successfully eliminate 28% refresh operations for a set of workloads on average.
Ying Wang Yinhe Han Huawei Li
SKL of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences University of Chinese Academy of Sciences Beijing, P.R.China
国际会议
昆明
英文
107-115
2014-05-01（万方平台首次上网日期，不代表论文的发表时间）